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Rebellions introduces REBEL-Quad and REBEL-IO—chiplet-based inference accelerators purpose-built for hyperscale and enterprise AI workloads. With a multi-chiplet architecture, HBM3e, and UCIe-Advanced interconnect, the system delivers exceptional compute density and energy efficiency, outperforming leading GPUs in throughput-per-watt across models like LLaMA-70B and 405B. The demo highlights single-card inference performance, demonstrating high efficiency and low power consumption even for large models. Powered by a production-ready software stack compatible with PyTorch, vLLM, and Triton, Rebellions offers a sustainable, deployable alternative for next-gen AI infrastructure.

Author:

Jinwook Oh

Co Founder and CTO
Rebellions

Jinwook Oh is the Co-Founder and Chief Technology Officer of Rebellions, an AI chip company based in South Korea. After earning his Ph.D. from KAIST (Korea Advanced Institute of Science and Technology), he joined the IBM TJ Watson Research Center, where he contributed to several AI chip R&D projects as a Chip Architect, Logic Designer, and Logic Power Lead. At Rebellions, he has overseen the development and launch of two AI chips, with a third, REBEL, in progress. Jinwook's technical leadership has been crucial in establishing Rebellions as a notable player in AI technology within just three and a half years.

... read more

Jinwook Oh

Co Founder and CTO
Rebellions

Jinwook Oh is the Co-Founder and Chief Technology Officer of Rebellions, an AI chip company based in South Korea. After earning his Ph.D. from KAIST (Korea Advanced Institute of Science and Technology), he joined the IBM TJ Watson Research Center, where he contributed to several AI chip R&D projects as a Chip Architect, Logic Designer, and Logic Power Lead. At Rebellions, he has overseen the development and launch of two AI chips, with a third, REBEL, in progress. Jinwook's technical leadership has been crucial in establishing Rebellions as a notable player in AI technology within just three and a half years.

Following the MLCommons Q3 MLPerf Inference results announcement on the morning of Tuesday 9th September on the keynote stage, Miro Hodak, Senior Member of Technical Staff, AI Performance Engineering at AMD will deliver a detailed analysis of the results followed by a Q&A session from the audience. 

Author:

Miro Hodak

Senior Member of Technical Staff, AI Performance Engineering
AMD

Miro Hodak is a Principal Member of Technical Staff at AMD, where he focuses on AI performance and benchmarking. Prior to joining AMD, he served as an AI Architect at Lenovo and was a professor in physics at North Carolina State University before that. 

Miro has been actively involved with MLPerf and MLCommons since 2020, contributing to the development of multiple MLPerf benchmarks and submitting results across several rounds of Inference and Training. Since 2023, he has served as co-chair of the MLPerf Inference Working Group.

He has authored peer-reviewed publications in fields ranging from artificial intelligence and computer science to materials science, physics, and biochemistry, with his work cited over 2,500 times.

... read more

Miro Hodak

Senior Member of Technical Staff, AI Performance Engineering
AMD

Miro Hodak is a Principal Member of Technical Staff at AMD, where he focuses on AI performance and benchmarking. Prior to joining AMD, he served as an AI Architect at Lenovo and was a professor in physics at North Carolina State University before that. 

Miro has been actively involved with MLPerf and MLCommons since 2020, contributing to the development of multiple MLPerf benchmarks and submitting results across several rounds of Inference and Training. Since 2023, he has served as co-chair of the MLPerf Inference Working Group.

He has authored peer-reviewed publications in fields ranging from artificial intelligence and computer science to materials science, physics, and biochemistry, with his work cited over 2,500 times.

Large language models can now power capable software agents, yet real‑world success comes from disciplined engineering rather than flashy frameworks. Most reliable agents are built from simple, composable patterns instead of heavy abstractions.


The talk will introduce patterns to add complexity and autonomy only when it pays off. Attendees should leave with a practical decision framework for escalating from a single prompt to multi‑step agents, also keeping in mind guardrails for shipping trustworthy, cost‑effective agents at scale. 

Author:

Sushant Mehta

Research Engineer
Google Deepmind
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Sushant Mehta

Research Engineer
Google Deepmind

Author:

Sherman Ikemoto

Group Director
Cadence

Sherman Ikemoto is the Sales Development Group Director at Cadence Design Systems, where he leads global business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as North America Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. During his tenure at Future Facilities, Sherman was a sought-after speaker at prominent industry events like ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a Bachelor of Science in Mechanical Engineering (BSME) from San Jose State University, where he was a member of the Tau Beta Pi engineering honor society, and a Master of Science in Mechanical Engineering (MSME) from Santa Clara University. His career reflects a deep commitment to advancing sustainable and efficient technologies for the data center industry.

... read more

Sherman Ikemoto

Group Director
Cadence

Sherman Ikemoto is the Sales Development Group Director at Cadence Design Systems, where he leads global business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as North America Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. During his tenure at Future Facilities, Sherman was a sought-after speaker at prominent industry events like ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a Bachelor of Science in Mechanical Engineering (BSME) from San Jose State University, where he was a member of the Tau Beta Pi engineering honor society, and a Master of Science in Mechanical Engineering (MSME) from Santa Clara University. His career reflects a deep commitment to advancing sustainable and efficient technologies for the data center industry.